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?products and specifications discussed here in are for evaluation and re ference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor features advance ? pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_1 rev. b 11/07 en 1 ?2007 micron technology, inc. all rights reserved. 1/4.5-inch 1.6mp cmos digital image sensor mt9m032 for the latest data sheet, refer to micron?s web site: www.micron.com/imaging features ? digitalclarity ? cmos imaging technology ? maximum frame rate (1284h x 812v/60 fps at 99 mhz) ? superior low-light performance ?low dark current ? global reset release (grr), which starts the exposure of all rows simultaneously ? simple two-wire serial interface ? programmable controls: gain, frame rate, frame size, exposure ? horizontal and vertical mirror image ? automatic black level calibration ? on-chip phase-locked loop (pll) oscillator ? bulb exposure mode for arbitrary exposure times ? snapshot mode to take frames on demand ? parallel data output ? electronic rolling shutter (ers), progressive scan ? arbitrary image decimati on with anti-aliasing ?programmable i/o slew rate ? programmable power-down mode (mode a or mode b) ? xenon and led flash support with fast exposure adaptation ? flexible support for external auto focus, optical zoom, and mechanical shutter ordering information table 1: available part numbers part number description mt9m032c12stces 48-pin pb-free clcc/color MT9M032C12STMUES 48-pin pb-free clcc/mono/ parallel mt9m032c12stmuhes 48-pin pb-free clcc/mono/ parallel headboard mt9m032c12stches 48-pin pb-free clcc/color/ parallel headboard mt9m032c12stcdes 48-pin pb-free color demo kit mt9m032c12stmudes 48-pin pb-free mono demo kit table 2: key performance parameters applications ? high definition surveillance camera ? high speed surveillance camera ?eptz camera parameter value optical format 1/4.5-inch (4:3) active imager size 3.24mm(h) x 2.41mm(v) active pixels 1472h x 1096v pixel size 2.2 x 2.2m color filter array rgb bayer pattern, mono shutter type global reset release (grr) (snapshot only), electronic rolling shutter (ers) maximum data rate/ master clock 99 mp/s / 49.5 mhz frame rate 1440h x 1080v programmable up to 30 fps 1280h x 720v programmable up to 60 fps adc resolution 12-bit, on-chip responsivity 1.4 v/lux-sec (550nm) 2.1 v/lux-sec (monochrome) dynamic range 70.1db snr max 38.1db supply voltage digital 1.7?1.9v i/o 2.6?3.1v pll 2.6?3.1v analog 2.6?3.1v power consumption 364.6mw at 2.8v operating temperature ?30c to +70c packaging 48-pin clcc
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 2 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor general description advance general description the micron ? imaging mt9m032 is a 1/4.5-inch form at cmos active-pixel digital image sensor with a pixel array of 1472h x 1096v. the default active imaging array size is 1440 x 1080. it incorporates sophisticated on-c hip camera functions such as windowing, mirroring, and snapshot mode. it is programmable through a simple two-wire serial interface and has very low power consumption. the mt9m032 digital image sensor features digitalclarity?micron?s breakthrough low- noise cmos imaging technology that achi eves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. functional overview the mt9m032 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single ma ster input clock running between 8 and 16.5 mhz. user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.6mp active-pixel array. the timing and control circuitry sequences through the rows of the array, resetting and then read ing each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the colu mns is sequenced through an analog signal chain (providing offset correction and gain), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provid es further data path corrections and applies digital gain). the pixel data are output at a rate of up to 99 mp/s, in addition to frame and line synchronization signals in parallel mo de corresponding to a pixel clock rate of 99 mhz. figure 1 shows the block diagram of the sensor. figure 1: block diagram ? parallel output d out [11:0] frame_valid line_valid pixclk sclk s data reset_bar extclk serial interface array control pixel array 1600h x 1152v data path analog signal chain
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 3 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor functional overview advance the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for on-chip offset correction algorithms (black level control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. the output from the sensor (mt9m032c12stc) is a bayer pa ttern; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain prov ide per-color control of the pixel data. a flash strobe output signal is provided to al low an external xenon or led light source to synchronize with the sensor exposure time an d to support the provision of an external mechanical shutter.
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 4 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions advance signal descriptions table 3 provides signal descriptions for the mt9m032. table 3: signal descriptions pin numbers name type description 26 sclk input serial clock. pull to v dd _io with a 1.5k resistor (depending on bus loading). 21 reset_bar input master reset sign al, active low. 33 extclk input input clock signal 8?49.5 mhz. 5 trigger input snapshot trigger. used to trigger one frame of ou tput in snapshot modes. 23, 25 test input enables manufacturing test modes. tie to digital gnd for functional operation. 45 s addr 0 input serial address. pull to v dd _io or d gnd to set serial address. 28 s addr 1 input serial address. pull to v dd _io or d gnd to set serial address. 27 s data i/o serial data. pull to v dd _io with a 1.5k resistor (depending on bus loading). 1 strobe output snapshot strobe. driven high when a ll pixels are exposi ng in snapshot modes. 4d out [0] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 48 d out [1] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 46 d out [2] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 20 d out [3] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 22 d out [4] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 24 d out [5] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 37 d out [6] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 35 d out [7] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 34 d out [8] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 38 d out [9] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 40 d out [10] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 41 d out [11] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. 47 pixclk output pixel clock. used to qu alify the line_valid (lv), frame_valid (fv), and d out (11:0). these outputs should be capt ured on the falling edge of this signal. 3 frame_valid output frame valid. qualified by pixclk. dr iven high during active pixels and horizontal blanking of each fram e and low during vertical blanking. 2 line_valid output line valid output. qualified by pixclk. dr iven high with active pixels of each line and low during horizontal blanking periods. external pull-down resistor to d gnd (typical 10k ?100k ) required for proper initialization sequence. 29, 44 v dd supply digital power 1.8v nominal.
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 5 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions advance figure 2: 48-pin clcc 10 x 10 package pinout diagram (top view) 10, 11 vaa_pix supply pixel array power 2.8v nominal. 7, 13, 18 v aa supply analog power 2.8v nominal. 32 v dd _pll supply pll power 2.8v nominal. 6, 19 v dd _io supply i/o power supply 2.8v nominal. 30, 31, 36, 39, 42, 43 d gnd supply digital ground. 8, 12, 17 a gnd supply analog ground. 9, 14, 15, 16 nc ? no connect. table 3: signal descriptions (continued) pin numbers name type description 1 2 3 4 5 6 4 84 7 4 6 4 5 44 43 19 20 21 22 23 24 25 2 6 27 28 29 30 7 8 9 10 11 12 13 14 15 1 6 17 18 42 41 40 39 38 37 3 6 35 34 33 32 31 v aa a g nd n c vaa_pix vaa_pix a g nd v aa n c n c n c a g nd v aa d g nd d out 11 d out 10 d g nd d out 9 d out 6 d g nd d out 7 d out 8 ext c lk v dd _pll d g nd v dd _io d out 3 re s et_bar d out 4 te s t d out 5 te s t sc lk s data s addr 1 v dd d g nd v dd _io tri gg er d out 0 frame_valid line_valid s trobe d out 1 pix c lk d out 2 s addr 0 v dd d g nd mt9m032 c l cc parallel (top view)
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 6 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor typical connections advance typical connections figure 3 shows typical connections for the mt9m032 sensor. for low-noise operation, the mt9m032 requires separate power supplies for analog and digital. incoming digital and analog ground conductors can be tied to gether next to the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals. the mt9m032 also supports different digital core (v dd /d gnd ) and i/o power (v dd _io/ d gnd ) power domains that can be at different voltages. pll requires a clean power source (v dd _pll). figure 3: typical configuration notes: 1. typical connection show s only one scenario out of mu ltiple possible variations for this sensor. 2. all inputs must be configured with v dd _io. 3. v aa and v aa _pix must be tied together. d out [11:0] frame_valid pix c lk s trobe line_valid n c re s et_bar sc lk s data tri gg er ext c lk v dd _io v dd v dd _pll v aa _pix v aa a g nd 10k 1.5k v dd _io v dd v dd _pll v aa 1f te s t d g nd from c ontroller master c lo c k to ima g e pro c essor (open) 1.5k 10k
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 7 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor pixel array structure advance pixel array structure the mt9m032 pixel array consists of a 160 0-column by 1152-row matrix of pixels addressed by column and row. the address (column 0, row 0) represents the upper-right corner of the entire array, looking at the sensor, as shown in figure 4. the array consists of a 1440-column by 10 80-row active region in the center repre- senting the default output image resolution, surrounded by a boundary region (also active), surrounded by a border of dark pixels (see table 4 and table 5). the boundary region can be used to avoid edge effects when doing color processing, while the optically black column and rows can be us ed to monitor the black level. default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 4). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in de fault condition is that of pixel (16,60). figure 4: pixel array description table 4: pixel type by column column pixel type 0?15 active boundary (16) 16?1455 active image (1440) 1456?1471 active boundary (16) 1472?1599 black (128) table 5: pixel type by row row pixel type 0?51 black (52) 53?59 active boundary (8) 60?1139 active image (1080) 1140?1147 active boundary (8) 1148?1151 black (4) (1599, 1151) 0 b la c k c olumns 4 b la c k rows 52 b la c k rows (0,0) 128 b la c k c olumns a c tive ima g e 1440 x 1080 a c tive pixels (1 6 , 6 0) (1455, 1139)
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 8 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor pixel array structure advance sensor pixels are output in a bayer pattern format consisting of four ?colors??greenr, greenb, red, and blue (gr, gb, r, b)?represe nting three filter colors. when no mirror modes are enabled, even-numbered rows contain alternate greenr and red pixels; odd- numbered rows contain alternate blue and greenb pixels. even-numbered columns contain greenr and blue pixels; odd-numbered columns contain red and greenb pixels. the greenr and greenb pixels have the same color filter, but they are treated as sepa- rate colors by the data path and analog signal chain. figure 5: pixel color pattern detail (top right corner) when the sensor is imaging, the active surface of the sensor faces the scene, as shown in figure 6. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced, as shown in figure 5. figure 6: imaging a scene first c lear pixel (0,52) bla c k pixels c olumn rea d out dire c tion . . . . . . ... row rea d out dire c tion r gb r gb r gb g r b g r b g r b r gb r gb r gb g r b g r b g r b r gb r gb r gb g r b g r b g r b lens pixel (0,0) row readout order column readout order scene sensor (rear view)
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 9 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor output data format advance output data format parallel pixel data interface mt9m032 image data is read out in a progre ssive scan. valid image data is surrounded by horizontal blanking and vertical blanking, as shown in figure 7. the amount of hori- zontal blanking and vertical blanking is pr ogrammable; lv is high during the shaded region of the figure. fv timing is described in the next section. figure 7: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 10 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor serial bus description advance serial bus description registers are written to and read from the mt9m032 through the two-wire serial inter- face bus. the mt9m032 is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the mt9m032 through the serial data (s data ) line. the s data line is pulled up to v dd _io off-chip by a 1.5k resistor. either the slave or master device can pull the s data line low?the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial defines several different transmission codes, as shown in the following sequence: 1. a start bit 2. the slave device 8-bit address 3. an (a no) acknowledge bit 4. an 8-bit message 5. a stop bit sequence a typical read or write sequence begins by the master sending a start bit. after the start bit, the master sends the slave device's 8-bit address. the last bit of the address determines if the request is a read or a wr ite, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. the mt9m032 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is automatically incremented after every 16 bits is trans- ferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high.
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 11 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor serial bus description advance stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb (least si gnificant bit) of the address indicates write mode (0xb8), and a ?1? indicates read mode (0xb9). the two-wire serial interface device addr esses consists of 7 bits. for the mt9m032 sensor, the device is fixed at [1011100]. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 12 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor features advance features pll-generated master clock the pll can generate a pixclk clock signal whose frequency is up to 99 mhz (input clock from 8?16.5 mhz). the pll-generated clock can be controlled by programming the appropriate register. it is possible to bypass the pll and use extclk as master clock. by default, the pll is powered up. the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and pll output divider stage to generate the output clock. the clocking structure is shown in figure 8. pll control can be programmed to generate desired pixel clock frequency. figure 8: pll-generated master clock note: the pll control registers must be programm ed while the sensor is in the software standby state. the effect of programming th e pll divisors while the sensor is in the streaming state is undefined. pll setup to use the pll: 1. bring the mt9m032 up as normal, ensure that f extclk is between 8 and 16.5 mhz. 2. set pll out divider to 7. (power-up default pll out divider setting is 6.) 3. set pll_m_factor and pll_n_divider based on the desired input ( f extclk) and out- put ( f pixclk) frequencies. using this formula: f pixclk = f vco/7 where f vco = ( f extclk x m) / n m = pll_m_factor, n = (pll_n_divider + 1) example of pll setting: f extclk = 13.5 mhz pll_m_factor = 0x9a (154), pll_n_divider = 0x02 f pixclk = 99 mhz 4. wait 1ms to ensure that the vco has locked. 5. set r0x10 = 0x0053 6. delay = 1ms 7. enable parallel data output 8. delay = 1ms ext c lk pll output c lo c k pll_n_divider +1 pre pll div (pfd) pll input c lo c k pll multiplier (v c o) pll output div pll_out_divider(6) pll_m_factor s ys c lk (pix c lk) n m
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 13 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor features advance maintaining a constant frame rate maintaining a constant frame rate while contin uing to have the ability to adjust certain parameters is often desired. this is not alwa ys possible, however, since register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. therefore, any register changes that could affect the row time or the set of rows sample d causes the shutter pointer to start over at the beginning of the next frame. by default, the following register fields caus e a "bubble" in the output rate (the vertical blank increases for one frame) if they are written in continuous mode, even if the new value would not change the resulting frame rate: ?row_start ? row_size ?column_size ?horizontal_blank ?vertical_blank ?shutter_delay ? mirror_row the size of this bubble is (sw t row), calculating the row time according to the new settings. the shutter_width_lower and shutter_widt h_upper fields may be written without causing a bubble in the output rate unde r certain circumstances. since the shutter sequence for the next frame often is active du ring the output of the current frame, this would not be possible without special provisio ns in the hardware. writes to these regis- ters take effect two frames after the frame they are written, which enables the shutter width to increase without interrupting the ou tput or producing a corrupt frame (as long as the change in shutter width does not affect the frame time). synchronizing register wr ites to frame boundaries changes to most register fields that affect th e size or brightness of an image take effect on the frame after the one during which they are written. to ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of fv and before the trailing edge of fv. as a special case, in snapshot modes (see belo w), register writes that occur after fv but before the next trigger will take effect imme diately on the next frame, as if there had been a restart. however, if the trigger for the next frame in ers snapshot mode occurs during fv, register writes take effect as with continuous mode. table 6: frequency parameters parameter equation min max unit pll_n_divider ? 0 63 pll_m_factor ? 16 255 f extclk ? 8 16.5 mhz f pfd f extclk /(pll_n_divider+1) 2 24 mhz f vco f extclk * pll_m_factor/ (pll_n_divider+1) 320 693 mhz
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 14 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor features advance additional control over the timing of register updates can be achieved by using synchronize_changes. if this bit is set, writes to certain register fields that affect the brightness of the output image do not take effect immediately. instead, the new value is remembered internally. when synchronize_changes is cleared, all the updates simulta- neously take effect on the next frame (as if they had all been written the instant synchronize_changes was cleared). fields not identified as being frame-synchronized or affected by synchronize_changes are update d immediately after the register write is completed. the effect of these registers on the next frame can be difficult to predict if they affect the shutter pointer. restart to restart the mt9m032 at any time during the operation of the sensor, write a ?1? to the restart register (r0x0b[0] = 1). this has two e ffects: first, the current frame is interrupted immediately. second, an y writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in continuous mode). register updates being held by synchronize_changes do not take effect until that bit is cleared. the current row and one following row complete before the new frame is started, so the time between issuing the restart and the begi nning of the next frame can vary by about t row. if pause_restart is set, rather than immedi ately beginning the next frame after a restart in continuous mode, the sensor pauses at the beginning of the next frame until pause_restart is cleared. this can be used to achieve a deterministic time period from clearing the pause_restart bit to the beginning of the first frame, meaning that the controller does not need to be tightly synchronized to lv or fv. note: when pause_restart is cleared, be sure to leave the restart register set to ?1? for proper operation. the restart bit will be cleared automatically by the device. window size the output image window of the pixel array (the fov) is programmable and defined by four register fields. column_start and row_ start define the x and y coordinates of the upper left corner of the fov. column_size defines the width of the fov, and row_size defines the height of the fov in array pixels. the column_start and row_start fields must be set to an even number. the column_size and row_size fields must be set to odd numbers (resulting in an even size for the fov). the row_start register should be set no lower than 12 if either manual_blc is cleared or show_dark_rows is set. the width of the output image, w, is column_size + 1 and height, h, is row_size + 1 . in default, a full resolution image size of 1440 x 1080 in output.
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_2 - rev. b 11/07 en 15 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor features advance image acquisition modes the mt9m032 supports two image acquisition modes (shutter types): electronic rolling shutter (ers), and global reset release (grr). electronic rolling shutter the ers modes take pictures by scanning the rows of the sensor. on the first scan, each row is released from reset, starting the exposure. on the second scan, the row is sampled, processed, and returned to the reset state. the exposure for any row is there- fore the time between the first and second sc ans. each row is exposed for the same dura- tion, but at slightly different point in time, which can cause a shear in moving subjects. whenever the mode is changed to an ers mode (even from another ers mode), and before the first frame following reset, there is an anti-blooming sequence where all rows are placed in reset. this sequence must complete before continuous readout begins. this delay is: t allreset = 16 1096 t aclk (where t aclk is 2 * t pixclk) global reset release the grr modes attempt to address the shearing effect by starting exposures of all rows at the same time. instead of the first scan used in ers mode, the reset to each row is released simultaneously. the second scan oc curs as normal, so th e exposure time for each row would different. typically, an external mechanical shutter would be used to stop the exposure of all rows simultaneously. in grr modes, there is a startup overhead be fore each frame as all rows are initially placed in the reset state ( t allreset). unlike ers mode, this delay always occurs before each frame. however, it occurs as soon as possible after the preceding frame, so typically the time from trigger to the start of exposure does not include this delay. to ensure that this is the case, the first trigger must occur no sooner than t allreset after the previous frame is read out.
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_3 - rev. b 11/07 en 16 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor spectral characteristics advance spectral characteristics figure 9: typical colo r spectral characteristics figure 10: typical monochrome spectral characteristics quantum effi c ien c y vs. wavelen g th 0 5 10 15 20 25 30 35 40 45 50 350 400 450 500 550 6 00 6 50 700 750 wavelen g th (nm) quantum effi c ien c y (%) b g r quantum effi c ien c y vs. wavelen g th 0 10 20 30 40 50 6 0 350 450 550 6 50 750 850 950 1050 wavelen g th (nm) quantum effi c ien c y (%)
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_3 - rev. b 11/07 en 17 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor dc electrical characteristics advance dc electrical characteristics table 7: dc electrical characteristics symbol parameter condition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 2.6 2.8 3.1 v v aa analog voltage 2.6 2.8 3.1 v v aa _pix pixel supply voltage 2.6 2.8 3.1 v v dd _pll pll supply voltage 2.6 2.8 3.1 v v ih input high voltage v dd _io = 2.8v v v il input low voltage v dd _io = 2.8v v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd ?<10 a v oh output high voltage at specified i oh v v ol output low voltage at specified i ol v i oh output high current at specified v oh ma i ol output low current at specified v ol ?ma i oz tri-state output leakage current v in = v dd _io or gnd ? a i dd digital operating current streaming, full resolution ? 28.0 ma i dd _io i/o digital operating current streaming, full resolution ? 27.3 ma i aa analog operating current streaming, full resolution ? 65.0 ma i aa _pix pixel supp ly current streaming, full resolution ? 5.6 ma i dd _pll pll supply current streaming, full resolution ? 3.0 ma i stby _a1 soft standby current clock off ? 0.21 ? ma i stby _b1 soft standby current clock off ? 32.31 ? ma i stby _a1 soft standby current clock off ? 0.21 ? ma i stby _b1 soft standby current clock off ? 28.41 ? ma table 8: power consumption - parallel at 30 fps, full resolution, 25c symbol parameter typ current (ma) typ voltage (v) power parallel (mw) p vdd digital operating power 28.0 1.8 50.4 p vddio 1 i/o digital operating power 7.7 2.8 21.6 p vddio 2 (parallel) i/o power parallel 19.6 2.8 86.5 p vaa analog operating power 65.0 2.8 182.0 p vaapix pll supply power 5.6 2.8 15.7 p vddpll pll supply power 3.0 2.8 8.4 p total total power 364.6
pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_3 - rev. b 11/07 en 18 ?2007 micron technology, inc. all rights reserved. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor dc electrical characteristics advance absolute maximum ratings caution stresses greater than those listed may cause pe rmanent damage to the device. exposure to absolute maximum rating co nditions for extended peri ods may affect reliability. notes: 1. this is a stress rating on ly, and functional operation of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. table 9: absolute maximum values symbol parameter condition min max unit v dd _ max core digital voltage ?0.3 1.9 v v dd _io_ max i/o digital voltage ?0.3 3.1 v v aa _ max analog voltage ?0.3 3.1 v v aa _pix_ max pixel supply voltage ?0.3 3.1 v v dd _pll_ max pll supply voltage ?0.3 3.1 v v in _ max input high voltage ?0.3 v dd _io + 0.3 v i dd _ max digital operating current worst case current ma i dd _io_ max i/o digital operating current worst case current ma i aa _ max analog operating current worst case current ma i aa _pix_ max pixel supply current worst case current ma i dd _pll_ max pll supply current worst case current ma t op operating temperature measure at junction ?30 70 c t stg storage temperature ?40 85 c
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, the micron logo, and di gitalclarity are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. advance: this data sheet contains initial de scriptions of products still under development. mt9m032: 1/4.5-inch 1.6mp cmos digital image sensor package dimensions pdf: 09005aef82bee26e/source: 09005aef82b99597 micron technology, inc., reserves the right to change products or specifications without notice. mt9m032_lds_3 - rev. b 11/07 en 19 ?2007 micron technology, inc. all rights reserved. advance package dimensions the 48-pin clcc package mechanical drawin g is illustrated in figure 11. the optical center is aligned with the package center as origin. figure 11: 48-pin clcc package outline notes: 1. all dimensions in millimeters. seating plane 4.4 11.43 0.2 5.215 10.43 lid material: borosilicate glass 0.55 thickness wall material: alumina ceramic substrate material: alumina ceramic 0.7 thickness 8.8 4.4 10.43 4.72 5.215 0.8 typ 2 0.2 0.8 typ 8.8 48 1 10.9 0.1 ctr 47x 1.0 0.2 48x r 0.15 48x 0.40 0.05 11.43 0.2 10.9 0.1 ctr 0.1 typ lead finish: au plating, 0.5 microns minimum thickness over ni plating, 1.27 microns minimum thickness 2.3 0.2 1.7 for reference only 1.2 for reference only first clear pixel optical center and package center c a b optical area optical area: maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 100 microns a d 1.27 for reference only 1.03 0.125 0.72 for reference only 2.376 ctr 4x r0.15 ?0.20 a c b 3.168 ctr ?0.20 a b c image sensor die: 0.305 thickness 0.10 a 0.05 4x 0.4

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